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| ht48r062/HT48C062 cost-effective i/o type 8-bit mcu block diagram rev. 1.11 1 october 30, 2006 features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 11 bidirectional i/o lines on-chip crystal and rc oscillator watchdog timer 1k 14 program memory 32 8 data ram halt function and wake-up feature reduce power consumption 63 powerful instructions up to 0.5 s instruction cycle with 8mhz system clock all instructions in 1 or 2 machine cycles 14-bit table read instructions one-level subroutine nesting bit manipulation instructions low voltage reset function 16-pin dip/nsop package general description the ht48r062/HT48C062 are 8-bit high performance, risc architecture microcontroller devices specifically designed for cost-effective multiple i/o control product applications. the mask version HT48C062 is fully pin and functionally compatible with the otp version ht48r062 devices. the advantages of low power consumption, i/o flexibil- ity, oscillator options, halt and wake-up functions, watchdog timer, as well as low cost, enhance the versa- tility of these devices to suit a wide range of application possibilities such as industrial control, consumer prod- ucts, subsystem controllers, etc. technical document tools information faqs application note ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom ha0013e ht48 & ht46 lcm interface design ha0016e writing and reading to the ht24 eeprom with the ht48 mcu series ha0018e controlling the ht1621 lcd controller with the ht48 mcu series ha0049e read and write control of the ht1380 ! " # $ % & # ' ( $ % ) ( # * + , - - % - - . / - . / 0 % * 1 ' pin assignment pin description pin name i/o code option description pa0~pa7 i/o pull-high wake-up bidirectional 8-bit input/output port. each bit can be configured as wake-up in - put by options. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high options). pb0~pb2 i/o pull-high bidirectional 3-bit input/output port. software instructions determine the cmos output or schmitt trigger input with a pull-high resistor (determined by pull-high options). vdd positive power supply vss negative power supply, ground osc2 osc1 o i crystal or rc osc1, osc2 are connected to an rc network or a crystal (determined by code option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock (nmos open drain output). res i schmitt trigger reset input. active low. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c iol total .............................................................150ma ioh total .......................................................... 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz 0.6 1.5 ma 5v 24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz 0.8 1.5 ma 5v 2.5 4 ma ht48r062/HT48C062 rev. 1.11 2 october 30, 2006 2 3 ( 4 . 5 4 ( 3 2 0 6 ( 3 2 0 4 . - . - - symbol parameter test conditions min. typ. max. unit v dd conditions i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz 48ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o port 0 0.3v dd v v ih1 input high voltage for i/o port 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset lvr enabled 2.7 3 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (rc osc) 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz t wdtosc watchdog oscillator period 3v 22 45 90 s 5v 16 32 64 s t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t lvr low voltage width to reset 0.25 1 2 ms note: t sys =1/f sys ht48r062/HT48C062 rev. 1.11 3 october 30, 2006 ht48r062/HT48C062 rev. 1.11 4 october 30, 2006 functional description execution flow the ht48r062/HT48C062 system clock can be derived from a crystal/ceramic resonator oscillator or an rc. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the 10-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted and its contents specify a maximum of 1024 ad - dresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. 4 ( 4 ( 4 ( 7 ! % 1 % ) , 8 % 1 % ) 9 , 7 ! % 1 % ) : , 8 % 1 % ) , 7 ! % 1 % ) : , 8 % 1 % ) : , : : % & # % & execution flow mode program counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000 skip program counter+2 loading pcl *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *9~*0: program counter bits s9~s0: stack register bits #9~#0: instruction code bits @7~@0: pcl bits ht48r062/HT48C062 rev. 1.11 5 october 30, 2006 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data and table and is organized into 1024 14 bits, ad - dressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for the initialization program. af - ter chip reset, the program always begins execution at location 000h. table location any location in the eprom space can be used as look-up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the desti - nation of the lower-order byte in the table is well-defined, the other bits of the table word are trans - ferred to the lower portion of tblh, the remaining 2 bits are read as 0 . the table higher-order byte reg - ister (tblh) is read only. the table pointer (tblp) is a read/write register (07h), where p indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. all table related instructions need 2 cy- cles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory used to save the contents of the program counter only. the stack is orga - nized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call the contents of the program counter are pushed onto the stack. at the end of a subroutine sig - naled by a return instruction (ret), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a call is subsequently exe - cuted, stack overflow occurs and the first entry will be lost (only the most recent return address is stored). data memory ram the data memory is designed with 44 8 bits. the data memory is divided into two functional groups: special function registers and general purpose data memory (32 8). most of them are read/write, but some are read only. the special function registers include the indirect ad - dressing register (00h), the memory pointer register (mp;01h), the accumulator (acc;05h) the program counter lower-order byte register (pcl;06h), the table pointer (tblp;07h), the table higher-order byte register (tblh;08h), the watchdog timer option setting register (wdts;09h), the status register (status;0ah), the i/o registers (pa;12h, pb;14h) and i/o control registers (pac;13h, pbc;15h). the remaining space before the 20h is reserved for future expanded usage and reading these locations will return the result 00h. the general purpose data memory, addressed from 20h to 3fh, is used for data and control information under instruction command. all data memory areas can handle arithmetic, logic, in - crement, decrement and rotate operations directly. ex - cept for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indi - rectly accessible through memory pointer register (mp;01h). . . . * ; % & + % < ( % = # 9 < % = & % ) 3 2 % > , . . * # 9 < % = & % ) 3 2 % > , 4 7 7 * 1 ? % % % " % . % % 4 7 7 * program memory instruction(s) table location *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *9~*0: table location bits @7~@0: table pointer bits p9~p8: current program counter bits ht48r062/HT48C062 rev. 1.11 6 october 30, 2006 indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data memory pointed to by mp (01h). reading location 00h itself indirectly will return the re - sult 00h. writing indirectly results in no operation. the memory pointer register mp (01h) is a 7-bit register. the bit 7 of mp is undefined and reading will return the result 1 . any writing operation to mp will only transfer the lower 7-bit data to mp. accumulator the accumulator closely relates to alu operations. it is also mapped to location 05h of the data memory and is capable of carrying out immediate data operations. data movement between two data memory locations has to pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions. arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the contents of the status register. status register status this 8-bit status register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and con- trols the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other register. any data written into the status register will not change the to or pdf flags. in addition it should be noted that operations related to the status register may give different results from those intended. the to and pdf flags can only be changed by the watchdog timer overflow, chip power-up, clearing the watchdog timer and executing the halt instruction. < & % < % % % - - * $ - - & % < % ) 4 % - , 2 * 7 * 4 7 * ? % @ % % a . . a . * . . * . * . * . 4 * . ( * . 3 * . 2 * . 0 * . 6 * . 5 * . * . - * . * . * . * . 7 * . * * * 4 * ( * 3 * ram mapping bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared when either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register ht48r062/HT48C062 rev. 1.11 7 october 30, 2006 the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on executing the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the sub - routine can corrupt the status register, precautions must be taken to save it properly. oscillator configuration there are two oscillator circuits implemented in the microcontroller. both are designed for system clocks; the rc oscillator and the crystal oscillator, which are determined by code options. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores the external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss in needed and the resistance must range from 24k to 1m . the system clock, divided by 4, is available on osc2, which can be used to synchro- nize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature and the chip itself due to process variations. it is, therefore, not suit- able for timing sensitive operations where accurate os - cillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift for the oscillator. no other external components are needed. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. watchdog timer wdt the clock source of wdt is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), decided by options. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by an op - tion. if the watchdog timer is disabled, all the execu - tions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 32 s at 5v normally) is selected, it is first di - vided by 512 (9-stage) to get the nominal time-out pe - riod of approximately 17ms at 5v. this time-out period may vary with temperatures, vdd and process varia - tions. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the di - vision ratio is up to 1:128, and the maximum time-out period is 2.1s at 5v seconds. if the wdt oscillator is dis - abled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its pro - tecting purpose. in this situation the logic can only be re - started by external logic. the high nibble and bit 3 of the wdts are reserved for user s defined flags, which can be used to indicate some specified status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset , and only the program counter and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res), software instruction and a halt in - & % & & % & & 1 % < % " b ' ( ( 0 . < 7 system oscillator % & # ' ( 6 9 = % $ % & 0 9 = % 6 9 9 % $ % 9 $ . / $ < & $ % ) ( # * + , watchdog timer ht48r062/HT48C062 rev. 1.11 8 october 30, 2006 struction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 .of these two types of instruction, only one can be active de - pending on the option clr wdt times selection op - tion .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator turns off and the wdt stops. the contents of the on-chip ram and registers remain unchanged. wdt prescaler are cleared. all i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can quit the halt mode by means of an ex - ternal reset or an external falling edge signal on port b. an external reset causes a device initialization. exam - ining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared when the system powers up or execute the clr wdt instruc- tion and is set when the halt instruction is executed. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp, the others keep their original status. the port a wake-up can be considered as a continua- tion of normal execution. each bit in port a can be inde- pendently selected to wake up the device by the code option. awakening from an i/o port stimulus, the pro - gram will resume execution of the next instruction. once a wake-up event(s) occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy cycle period will be inserted after the wake-up. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation some registers remain unchanged during reset condi - tions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged. to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem powers up or when the system awakes from a halt state. when a system power up occurs, an sst delay is added during the reset period. but when the reset comes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional unit chip reset status is shown below. program counter 000h wdt prescaler clear input/output ports input mode stack pointer points to the top of the stack $ $ 9 * > 9 % . 9 < < & % reset configuration reset circuit % 9 ! < % % reset timing chart ht48r062/HT48C062 rev. 1.11 9 october 30, 2006 input/output ports there are up to 11 bidirectional input/output lines in the microcontroller labeled with port names pa and pb, which are mapped to the data memory of [12h] and [14h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h or 14h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. to function as an input, the corresponding latch of the con- trol register must write 1 . the input source also de- pends on the control register. if the control register bit is 1 , the input will read the pad state. if the control regis- ter bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify- write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h and 15h. the chip reset status of the registers is summarized in the following table: register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* program counter 000h 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu pbc ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu note: * means warm reset u means unchanged x means unknown . / 0 - . / - $ # 9 < % < % $ # 9 < ) % & , % % c d & % - & & 9 ! ! % - $ % & % ! < % % & % $ % % % - c c d c input/output ports ht48r062/HT48C062 rev. 1.11 10 october 30, 2006 after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h or 14h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the highest 5-bit of port b are not physically im - plemented; on reading them a 0 is returned whereas writing then results in a no-operation. see application note. there are pull-high options available for pa and pb. once the pull-high option is selected, i/o lines have pull-high resistors. otherwise, the pull-high resistors are absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera- tion at 4mhz system clock. 3 e 3 4 e . e . e 5 3 e 3 3 e 3 . e 5 . % & f f 1 & % < % % & low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. application circuits note: the resistance and capacitance for reset circuit should be designed to ensure that the v dd is stable and re- mains in a valid range of the operating voltage before bringing res high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for refer - ence only) crystal or resonator c1, c2 r1 4mhz crystal 25pf 10k 4mhz resonator 10pf 12k 3.58mhz crystal 25pf 10k 3.58mhz resonator 25pf 10k 2mhz crystal 30pf 12k 2mhz resonator 25pf 12k 1mhz crystal 100pf 10k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k 400khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. ht48r062/HT48C062 rev. 1.11 11 october 30, 2006 options the following table shows eight kinds of code option in the ht48r062/HT48C062. all the code options must be defined to ensure proper system functioning. no. options 1 wdt clock source: wdtosc or f sys /4 2 wdt function: enable or disable 3 lvr function: enable or disable 4 clrwdt instruction(s): one or two clear wdt instruction(s) 5 system oscillator: rc or crystal 6 pa and pb pull-high resistors: none or pull-high 7 pa0~pa7 wake-up: enable or disable . / 0 - . / - . e 7 f . . # . e 7 . e . 7 f . # ! " 7 % ! % ; & @ % = & % = & > ! " ( # g g ! # 1 % < % " b ' ( ( 0 . < 7 instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht48r062/HT48C062 rev. 1.11 12 october 30, 2006 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht48r062/HT48C062 rev. 1.11 13 october 30, 2006 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 14 october 30, 2006 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 15 october 30, 2006 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 16 october 30, 2006 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 17 october 30, 2006 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 18 october 30, 2006 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 19 october 30, 2006 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 20 october 30, 2006 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 21 october 30, 2006 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 22 october 30, 2006 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 23 october 30, 2006 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 24 october 30, 2006 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 25 october 30, 2006 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht48r062/HT48C062 rev. 1.11 26 october 30, 2006 package information 16-pin dip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 745 775 b 240 260 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 335 375 0 15 ht48r062/HT48C062 rev. 1.11 27 october 30, 2006 % % 2 5 6 - 7 * 16-pin nsop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228 244 b 149 157 c14 20 c 386 394 d53 69 e 50 f4 10 g22 28 h4 12 0 10 ht48r062/HT48C062 rev. 1.11 28 october 30, 2006 2 5 6 - 7 * h product tape and reel specifications reel dimensions sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 62 1.5 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 16.8+0.3 0.2 t2 reel thickness 22.2 0.2 ht48r062/HT48C062 rev. 1.11 29 october 30, 2006 - carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16 0.3 p cavity pitch 8 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.3 0.05 c cover tape width 13.3 ht48r062/HT48C062 rev. 1.11 30 october 30, 2006 $ . 7 d . - . . ht48r062/HT48C062 rev. 1.11 31 october 30, 2006 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 0755-8616-9908, 8616-9308 fax: 0755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 028-6653-6590 fax: 028-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com copyright 2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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